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? freescale semiconductor, inc., 2005. all rights reserved. this document contains information on a new produc t. specifications and information herein are subject to change without notice. freescale semiconductor advance information mc9328mxs/d rev. 0, 1/2005 mc9328mxs package information plastic package (pbga?225) ordering information see table 2 on page 4 mc9328mxs 1 introduction the i.mx (media extensions ) series provides a leap in performance with an arm9? microprocessor core and highly integrated system functions. the i.mx products specifically address the requi rements of the personal, portable product market by pr oviding intelligent integrated peripherals, an advanced processor core, and power management capabilities. the i.mx processor features the advanced and power- efficient arm920t? core that operates at speeds up to 100 mhz. integrated modules, which include a usb device and an lcd controller, support a suite of peripherals to enhance portable products. it is packaged in a 225-contact pbga package. figure 1 shows the functional block diagram of the i.mx processor. contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 signals and connections . . . . . . . . . . . . . . . . . . . .5 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pin-out and package information . . . . . . . . . . . .69 contact information . . . . . . . . . . . . . . . . . last page
mc9328mxs advance information, rev. 0 2 freescale semiconductor introduction figure 1. mc9328mxs functional block diagram 1.1 conventions this document uses the following conventions: ? overbar is used to indicate a signal that is active when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conv eys or changes in stat e convey information. ?a pin is an external physical connec tion. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic le vel zero to logic level one. ? negated means that an asserted discret e signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic le vel one to logic level zero. ? lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are bi nary. numbers preceded by a dollar sign ($) or 0x are hexadecimal.
introduction mc9328mxs advance information, rev. 0 freescale semiconductor 3 1.2 features to support a wide variety of applica tions, the i.mx processor offers a robu st array of features, including the following: ? arm920t? microprocessor core ? ahb to ip bus interfaces (aipis) ? external interface module (eim) ? sdram controller (sdramc) ? dpll clock and powe r control module ? two universal asynchronous receiv er/transmitters (uart 1 and uart 2) ? serial peripheral interface (spi) ? two general-purpose 32-bit counters/timers ? watchdog timer ? real-time clock/sampling timer (rtc) ? lcd controller (lcdc) ? pulse-width modulation (pwm) module ? universal serial bus (usb) device ? direct memory access controller (dmac) ? synchronous serial interfa ce and inter-ic sound (ssi/i 2 s) module ? inter-ic (i 2 c) bus module ? general-purpose i/o (gpio) ports ? bootstrap mode ? power management features ? operating voltage range: 1.7 v to 1.9 v core, 1.7 v to 3.3 v i/o ? 225-contact pbga package 1.3 target applications the i.mx processor is targeted for ad vanced information appliances, smart phones, web browsers, and messaging applications. 1.4 revision history table 1 provides revision history for th is release. this history includes tec hnical content revisions only and not stylistic or grammatical changes. table 1. mc9328mxs data sheet revision history for rev. 0 revision initial release
mc9328mxs advance information, rev. 0 4 freescale semiconductor introduction 1.5 reference documents the following documents are required for a complete de scription of the mc9328mxs and are necessary to design properly with the device. especially for those not familiar with the arm9 20t processor or previous dragonball products, the following documents are helpful when used in co njunction with this document. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) arm technical reference manual (arm ltd., order number arm ddi 0151c) emt9 technical reference manual (arm ltd., order number ddi o157e) mc9328mxs product brief (order number mc9328mxsp/d) mc9328mxs reference manual (order number mc9328mxsrm/d) the freescale manuals are available on the freescale semiconductors web site at http://www.freescale.com/imx. these documents may be downloaded directly from the freescale web site, or printed versions may be ordered. the arm ltd. documentation is available from http://www.arm.com. 1.6 ordering information table 2 provides ordering informatio n for the 225-contact pbga package. table 2. mc9328mxs ordering information package type frequency temperatu re solderball type order number 225-contact pbga 100 mhz -40 o c to 85 o c standard mc9328mxscvf10(r2) pb-free see note 1 1. contact your distribution center or freescale sales office. 0 o c to 70 o c standard mc9328mxsvf10(r2) pb-free see note 1
signals and connections mc9328mxs advance information, rev. 0 freescale semiconductor 5 2 signals and connections table 3 identifies and describes the i.mx processor signal s that are assigned to package pins. the signals are grouped by the internal module that they are connected to. table 3. mc9328mxs signal descriptions signal name function/notes external bus/chip-select (eim) a[24:0] address bus signals d[31:0] data bus signals eb0 msb byte strobe?active low external enable byte signal that controls d [31:24]. eb1 byte strobe?active low external enable byte signal that controls d [23:16]. eb2 byte strobe?active low external enable byte signal that controls d [15:8]. eb3 lsb byte strobe?active low external enable byte signal that controls d [7:0]. oe memory output enable?active low output enables external data bus. cs [5:0] chip-select?the chip-select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr). by default csd [1:0] is selected. ecb active low input signal sent by a flash device to the eim whenever the flas h device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by a flash device causing t he external burst device to latch the starting burst address. bclk (burst clock) clock signal sent to external synchronous memori es (such as burst flash) during burst mode. rw rw signal?indicates whether extern al access is a read (high) or write (low) cycle. used as a we input signal by external dram. dtack dtack signal?the external input data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 clock counts have elapsed. bootstrap boot [3:0] system boot mode select?the o perational system boot mode of the i.mx processor upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram non-interleave mode bank address mult iplexed with address si gnals a [15:11]. these signals are logically equivalent to core address p_addr [25:21] in sdram cycles. sdiba [3:0] sdram interleave addressing mode bank address mu ltiplexed with address signals a [19:16]. these signals are logically equivalent to core address p_addr [12:9] in sdram cycles. ma [11:10] sdram address signals ma [9:0] sdram address signals which are multiplexed with ad dress signals a [10:1]. ma [9:0] are selected on sdram cycles. dqm [3:0] sdram data enable csd0 sdram chip-select signal which is multiplexed with the cs2 signal. these two signals are selectable by programming t he system control register. csd1 sdram chip-select signal which is multiplexed with cs3 signal. these two signals are selectable by programming the system contro l register. by default, csd1 is selected, so it can be used as boot chip-select by properly confi guring boot [3:0] input pins. ras sdram row address select signal
mc9328mxs advance information, rev. 0 6 freescale semiconductor signals and connections cas sdram column address select signal sdwe sdram write enable signal sdcke0 sdram clock enable 0 sdcke1 sdram clock enable 1 sdclk sdram clock reset_sf not used clocks and resets extal16m crystal input (4 mhz to 16 mhz), or a 16 mhz oscillat or input when the internal oscillator circuit is shut down. xtal16m crystal output extal32k 32 khz crystal input xtal32k 32 khz crystal output clko clock out signal selected from internal clock signals. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module and the clock control module) are reset. reset_out reset out?internal active low output signal from the watchdog timer module and is asserted from the following sources: power-on reset, external reset (reset_in ), and watchdog time-out. por power on reset?internal active high schmitt tri gger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. jtag trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and control register access through the jtag port. tms test mode select to sequence the jtag test cont roller?s state machine. sampled on the rising edge of tck. dma big_endian big endian?input signal that determines the configurat ion of the external chip-select space. if it is driven logic-high at reset, the external chip-select sp ace will be configured to little endian. if it is driven logic-low at reset, the external chip -select space will be configured to big endian. dma_req external dma request pin. etm etmtracesync etm sync signal which is multiplexed with a24. etmtracesync is selected in etm mode. etmtraceclk etm clock signal which is multiplexed with a23. etmtraceclk is selected in etm mode. etmpipestat [2:0] etm status signals which are mu ltiplexed with a [22:20]. etmpipestat [2 :0] are selected in etm mode. etmtracepkt [7:0] etm packet signals which are multiplexed with ecb , lba , bclk(burst clock), pa17, a [19:16]. etmtracepkt [7:0] are selected in etm mode. lcd controller ld [15:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. table 3. mc9328mxs signal descriptions (continued) signal name function/notes
signals and connections mc9328mxs advance information, rev. 0 freescale semiconductor 7 flm/vsync frame sync or vsync?this signal also serves as the clock signal output for the gate driver (dedicated signal sps for sharp panel hr-tft). lp/hsync line pulse or h sync lsclk shift clock acd/oe alternate crystal di rection/output enable. contrast this signal is used to control the lcd bias voltage as contrast control. spl_spr program horizontal scan direction (sharp panel dedicated signal). ps control signal output for source driver (sharp panel dedicated signal). cls start signal output for gate driver . this signal is an inverted version of ps (sharp panel dedicated signal). rev signal for common electrode driving signal pr eparation (sharp panel dedicated signal). spi 1 spi1_mosi master out/slave in spi1_miso slave in/master out spi1_ss slave select (selectable polarity) spi1_sclk serial clock spi1_spi_rdy serial data ready general purpose timers tin timer input capture or timer input clock?the signal on this input is ap plied to both timers simultaneously. tmr2out timer 2 output usb device usbd_vmo usb minus output usbd_vpo usb plus output usbd_vm usb minus input usbd_vp usb plus input usbd_suspnd usb suspend output usbd_rcv usb receive data usbd_oe usb oe usbd_afe usb analog front end enable uarts ? irda/auto-bauding uart1_rxd receive data uart1_txd transmit data uart1_rts request to send uart1_cts clear to send uart2_rxd receive data uart2_txd transmit data uart2_rts request to send uart2_cts clear to send uart2_dsr data set ready table 3. mc9328mxs signal descriptions (continued) signal name function/notes
mc9328mxs advance information, rev. 0 8 freescale semiconductor signals and connections uart2_ri ring indicator uart2_dcd data carrier detect uart2_dtr data terminal ready serial audio port ? ssi (configurable to i 2 s protocol) ssi_txdat transmit data ssi_rxdat receive data ssi_txclk transmit serial clock ssi_rxclk receive serial clock ssi_txfs transmit frame sync ssi_rxfs receive frame sync i 2 c i2c_scl i 2 c clock i2c_sda i 2 c data pwm pwmo pwm output test function tristate forces all i/o signals to high impedance for test purposes. for normal operation, terminate this input with a 1 k ohm resistor to ground. (tri-state ? is a registered trademark of national semiconductor.) general purpose input/output pa[14:3] dedicated gpio pb[13:8] dedicated gpio digital supply pins nvdd digital supply for the i/o pins nvss digital ground for the i/o pins supply pins ? analog modules avdd supply for analog blocks avss quiet ground for analog blocks internal power supply qvdd power supply pins for silicon internal circuitry qvss ground pins for silicon internal circuitry substrate supply pins svdd supply routed through substrate of package; not to be bonded sgnd ground routed through substrate of package; not to be bonded table 3. mc9328mxs signal descriptions (continued) signal name function/notes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 9 3 specifications this section contains the electrical specificatio ns and timing diagrams for the i.mx processor. 3.1 maximum ratings table 4 provides information on maxi mum ratings which are those values beyond which damage to the device may occur. functional operation sh ould be restricted to the limits listed in recommended operating range table 5 on page 9 or the dc characteristics table. 3.2 recommended operating range table 5 provides the recommended oper ating ranges for the supply voltages a nd temperatures. the i.mx processor has multiple pairs of vdd and vss power supply and re turn pins. qvdd and qvss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provides power to the enclosed i/o pads. this design allows different peripheral supply voltage levels in a system. because avdd pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the avdd pins from other vdd pins. for more information about i/o pads groupi ng per vdd, please refer to table 3 on page 5. table 4. maximum ratings symbol rating minimum maximum unit nvdd dc i/o supply voltage -0.3 3.3 v qvdd dc internal (core = 100 mhz) supply voltage -0.3 1.9 v avdd dc analog supply voltage -0.3 3.3 v btrfvdd dc bluetooth supply voltage -0.3 3.3 v vesd_hbm esd immunity with hbm (human body model) ? 2000 v vesd_mm esd immunity with mm (machine model) ? 100 v ilatchup latch-up immunity ? 200 ma test storage temperature -55 150 c pmax power consumption 800 1 1. a typical application with 30 pads simultaneously swit ching assumes the gpio toggling and instruction fetches from the arm ? core-that is, 7x gpio, 15x data bus, and 8x address bus. 1300 2 2. a worst-case application with 70 pads simultaneously s witching assumes the gpio toggling and instruction fetches from the arm core-that is, 32x gpio, 30x data bus, 8x address bus. these calculations are based on the core running its heaviest os application at 100mhz, and wher e the whole image is running out of sdram. qvdd at 1.9v, nvdd and avdd at 3.3v, therefore, 180ma is the wo rst measurement recorded in the factory environment, max 5ma is consumed for osc pads, wit h each toggle gpio consuming 4ma. mw table 5. recommended operating range symbol rating minimum maximum unit t a operating temperature range mc9328mxsvf10 070c
mc9328mxs advance information, rev. 0 10 freescale semiconductor specifications 3.3 power sequence requirements for required power-up and power-down sequencing, please refer to the "power-up sequen ce" section of application note an2537 on the i.mx application processor website. 3.4 dc electrical characteristics table 6 contains both maximu m and minimum dc characteristics of the i.mx processor. t a operating temperature range mc9328mxscvf10 -40 85 c nvdd i/o supply voltage (if using spi, lcd, and usbd which are only 3 v interfaces) 2.70 3.30 v nvdd i/o supply voltage (if not using the peripherals listed above) 1.70 3.30 v qvdd internal supply voltage (core = 100 mhz) 1.70 1.90 v avdd analog supply voltage 1.70 3.30 v table 6. maximum and minimum dc characteristics number or symbol parameter min typical max unit iop full running operating current at 1.8v for qvdd, 3.3v for nvdd/avdd (core = 96 mhz, system = 96 mhz, driving tft display panel, and os with mmu enabled memory system is running on external sdram). ? qvdd at 1.8v = 120ma; nvdd+avdd at 3.0v = 30ma ?ma sidd 1 standby current (core = 100 mhz, qvdd = 1.8v, temp = 25 c) ?25 ? a sidd 2 standby current (core = 100 mhz, qvdd = 1.8v, temp = 55 c) ?45 ? a sidd 3 standby current (core = 100 mhz, qvdd = 1.9v, temp = 25 c) ?35 ? a sidd 4 standby current (core = 100 mhz, qvdd = 1.9v, temp = 55 c) ?60 ? a v ih input high voltage 0.7v dd ?vdd+0.2v v il input low voltage ? ? 0.4 v v oh output high voltage (i oh = 2.0 ma) 0.7v dd ?vddv v ol output low voltage (i ol = -2.5 ma) ? ? 0.4 v i il input low leakage current (v in = gnd, no pull-up or pull-down) ??1 a table 5. recommended operating range (continued) symbol rating minimum maximum unit
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 11 3.5 ac electrical characteristics the ac characteristics consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other sign als. all timing specifications are specified at a system operating frequency from 0 mhz to 96 mhz (core operating frequency 100 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at 30 pf loading. i ih input high leakage current (v in =v dd , no pull-up or pull-down) ??1 a i oh output high current (v oh =0.8v dd , v dd =1.8v) ??4.0ma i ol output low current (v ol =0.4v, v dd =1.8v) -4.0 ? ? ma i oz output leakage current (v out =v dd , output is high impedence) ??5 a c i input capacitance ? ? 5 pf c o output capacitance ? ? 5 pf table 7. tristate signal timing pin parameter minimum maximum unit tristate time from tristate activate until i/o becomes hi-z ? 20.8 ns table 8. 32k/16m oscillator signal timing parameter minimum rms maximum unit extal32k input jitter (peak to peak) ? 5 20 ns extal32k startup time 800 ? ? ms extal16m input jitter (peak to peak) 1 1. the 16 mhz oscillator is not recommended for use in new designs. ?tbdtbd? extal16m startup time 1 tbd ? ? ? table 6. maximum and minimum dc characteristics (continued) number or symbol parameter min typical max unit
mc9328mxs advance information, rev. 0 12 freescale semiconductor specifications 3.6 embedded trace macrocell all registers in the etm9 are prog rammed through a jtag interface. the interface is an extension of the arm920t processor?s tap controller, a nd is assigned scan chain 6. the sca n chain consists of a 40-bit shift register comprised of the following: ? 32-bit data field ? 7-bit address field ? a read/write bit the data to be written is scan ned into the 32-bit data field, the address of the register in to the 7-bit address field, and a 1 into the read/write bit. a register is read by scanning its address into the address fi eld and a 0 into the read/write bit. the 32-bit data field is ignored. a read or a write takes place when the tap controller enters the update-dr state. the timing diagram for the etm9 is shown in figure 2. see tabl e 9 for the etm9 timing para meters used in figure 2. figure 2. trace port timing diagram table 9. trace port timi ng diagram parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 clk frequency 0 85 0 100 mhz 2a clock high time 1.3 ? 2 ? ns 2b clock low time 3 ? 2 ? ns 3a clock rise time ? 4 ? 3 ns 3b clock fall time ? 3 ? 3 ns 4a output hold time 2.28 ? 2 ? ns 4b output setup time 3.42 ? 3 ? ns traceclk 4b 4a 3b 2a 1 output trace port 3a valid data valid data 2b traceclk (half-rate clocking mode)
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 13 3.7 dpll timing specifications parameters of the dpll are given in table 10. in this table, t ref is a reference clock period after the pre-divider and t dck is the output double clock period. table 10. dpll specifications parameter test conditions minimum typical maximum unit reference clock freq range vcc = 1.8v 5 ? 100 mhz pre-divider output clock freq range vcc = 1.8v 5 ? 30 mhz double clock freq range vcc = 1.8v 80 ? 220 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5 ? 15 ? mf integer part ? 5 ? 15 ? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? pre-multiplier lock-in time ? ? ? 312.5 sec freq lock-in time after full reset fol mode for non-integer mf (does not include pre-multi lock-in time) 250 280 (56 s) 300 t ref freq lock-in time after partial reset fol mode for non-integer mf (does not include pre-multi lock-in time) 220 250 (50 s) 270 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-multi lock-in time) 300 350 (70 s) 400 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-multi lock-in time) 270 320 (64 s) 370 t ref freq jitter (p-p) ? ? 0.005 (0.01%) 0.01 2t dck phase jitter (p-p) integer mf, fpl mode, vcc=1.8v ? 1.0 (10%) 1.5 ns power supply voltage ? 1.7 ? 2.5 v power dissipation fol mode, integer mf, f dck = 100 mhz, vcc = 1.8v ?? 4mw
mc9328mxs advance information, rev. 0 14 freescale semiconductor specifications 3.8 reset module the timing relationships of the rese t module with the por and reset_in are shown in figure 3 and figure 4. note: be aware that nvdd must ramp up to at least 1.8v before qvdd is powered up to prevent forward biasing. figure 3. timing relationship with por por reset_por reset_dram hreset reset_out clk32 hclk 90% avdd 10% avdd 1 2 3 4 exact 300ms 7 cycles @ clk32 14 cycles @ clk32
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 15 figure 4. timing relationship with reset_in table 11. reset module timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min max min max 1 width of input power_on_reset note 1 1. por width is dependent on the 32 or 32.768 khz crystal o scillator start-up time. design margin should allow for crystal tolerance, i.mx chip variatio ns, temperature impact, and supply volt age influence. through the process of supplying crystals for use with cmos oscillators, crysta l manufacturers have developed a working knowledge of start-up time of their crystals. typically, start-up times r ange from 400 ms to 1.2 seconds for this type of crystal. if an external stable clock source (already running) is used instead of a crystal, the width of por should be ignored in calculating timing for the start-up process. ? note 1 ?? 2 width of internal power_on_reset (clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher fo r sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretcher for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4 ? 4 ? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6
mc9328mxs advance information, rev. 0 16 freescale semiconductor specifications 3.9 external interface module the external interface module (eim) handles the interface to devices external to the i. mx processor, including the generation of chip-selects for external peripherals an d memory. the timing diagram for the eim is shown in figure 5, and table 12 on page 16 defines the parameters of signals. figure 5. eim bus timing diagram table 12. eim bus timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min typical max min typical max 1a clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns 1b clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) bclk (burst clock) - rising edge lba (negated falling edge) eb (falling edge) eb (rising edge) bclk (burst clock) - falling edge read data write data (negated falling) write data (negated rising) dtack_b 10a 10a
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 17 2a clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns 2b clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns 3a clock fall to read (write ) valid 1.35 2.79 6.52 1.3 2.7 6.3 ns 3b clock fall to read (write ) invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns 4a clock 1 rise to output enable valid 2.32 2.62 6.85 2.3 2.6 6.8 ns 4b clock 1 rise to output enable invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns 4c clock 1 fall to output enable valid 2.38 2.69 7.04 2.3 2.6 6.8 ns 4d clock 1 fall to output enable invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns 5a clock 1 rise to enable bytes valid 1.91 2.52 5.54 1.9 2.5 5.5 ns 5b clock 1 rise to enable bytes invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns 5c clock 1 fall to enable bytes va lid 1.97 2.59 5.69 1.9 2.5 5.5 ns 5d clock 1 fall to enable bytes in valid 1.76 2.48 5.38 1.7 2.4 5.2 ns 6a clock 1 fall to load burst address valid 2.07 2.79 6.73 2.0 2.7 6.5 ns 6b clock 1 fall to load burst address invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns 6c clock 1 rise to load burst address invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns 7a clock 1 rise to burst clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns 7b clock 1 rise to burst clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns 7c clock 1 fall to burst clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns 7d clock 1 fall to burst clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns 8a read data setup time 5.54 ? ? 5.5 ? ? ns 8b read data hold time 0 ? ? 0 ? ? ns 9a clock 1 rise to write data valid 1.81 2.72 6.85 1.8 2.7 6.8 ns 9b clock 1 fall to write data inva lid 1.45 2.48 5.69 1.4 2.4 5.5 ns 9c clock 1 rise to write data invalid 1.63 ? ? 1.62 ? ? ns 10a dtack setup time 2.52 ? ? 2.5 ? ? ns 1. clock refers to the system clock signal , hclk, generated from the system dpll table 12. eim bus timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min typical max min typical max
mc9328mxs advance information, rev. 0 18 freescale semiconductor specifications 3.9.1 dtack signal description the dtack signal is the external input data acknow ledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-ou t monitor generates a bus error when a bus cycle is not te rminated by the external dtack signal after 1022 hclk counts have elapsed. only the cs5 group supports dtack signal function when the external dtack signal is used for data acknowledgement. 3.9.2 dtack signal timing figure 6 through figure 9 show the access cycle timing used by chip-select 5. the signal values and units of measure for this figure are found in the associated tables.
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 19 3.9.2.1 dtack read cycle without dma figure 6. dtack read cycle without dma table 13. read cycl e without dma: wsc = 11 1111, dtack_sel=0, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1 oe and eb assertion time see note 3 ? ns 2 cs5 pulse width 3t ? ns 3 oe negated to address inactive 46.39 ? ns 4 d tack asserted after cs5 asserted ? 1019t ns 5 d tack asserted to oe negated 3t+1.83 4t+6.6 ns 6 data hold timing after oe negated 0?ns 7 data ready after dtack asserted 0tns 8 oe negated to cs negated 0.5t-0.68 0.5t-0.06 ns 9 oe negated after eb negated 0.06 0.18 ns 10 dtack pulse width 1t 3t ns note : 1. dtack asserted means d tack becomes low level. 2. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 3. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 4. address becomes valid and cs asserts at the star t of read access cycle. 5. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. dtack address eb cs5 oe programmable min 0ns 3 2 9 (input to i.mx) 5 1 4 6 10 7 databus 8
mc9328mxs advance information, rev. 0 20 freescale semiconductor specifications 3.9.2.2 dtack read cycle dma enabled figure 7. dtack r ead cycle dma enabled table 14. read cycle dma enable d: wsc = 111111, dtack_sel=0, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1oe and eb assertion time see note 3 ? ns 2cs pulse width 3t ? ns 3oe negated before cs5 is negated 0.5t-0.68 0.5t-0.06 ns 4 address inactive before cs negated ? 0.3 ns 5d tack asserted after cs5 asserted ? 1019t ns 6d tack asserted to oe negated 3t+1.83 4t+6.6 ns 7 data hold timing after oe negated 0 ? ns 8 data ready after dtack is asserted ? t ns 9cs deactive to next cs active t ? ns 10 oe negate after eb negate 0.06 0.18 ns 11 dtack pulse width 1t 3t ns note : 1. dtack asserted means d tack becomes low level. 2. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 3. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 4. address becomes valid and cs asserts at the start of read access cycle. 5. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. rw dtack address eb cs5 oe (logic high) programmable min 0ns (input to i.mx) 2 8 9 1 4 6 10 11 databus 3 7 5
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 21 3.9.2.3 dtack writ e cycle without dma figure 8. dtack write cycle without dma table 15. write cycle without dma: wsc = 111111, dtack_sel=0, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1cs5 assertion time see note 3 ? ns 2eb assertion time see note 3 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 1.5t-2.44 1.5t-0.8 ns 5rw negated to address inactive 57.31 ? ns 6d tack asserted after cs5 asserted ? 1019t ns 7d tack asserted to rw negated 2t+2.37 3t+6.6 ns 8 data hold timing after rw negated 1.5t-3.99 ? ns 9 data ready after cs5 is asserted ? t ns 10 eb negated after c s5 is negated 0.5t 0.5t+0.5 ns 11 dtack pulse width 1t 3t ns note : 1. dtack asserted means d tack becomes low level. 2. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 3. cs5 assertion can be controlled by csa bits. eb assertion can also be programmed by wea bits in the cs5l register. 4. address becomes valid and rw asserts at the star t of write access cycle. 5. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. oe dtack address eb cs5 rw (logic high) programmable min 0ns programmable min 0ns (input to i.mx) 3 2 9 5 1 6 10 7 11 databus 4 8
mc9328mxs advance information, rev. 0 22 freescale semiconductor specifications 3.9.2.4 dtack writ e cycle dma enabled figure 9. dtack write cycle dma enabled table 16. write cycle dma enabled: wsc = 111111, dtack_sel=0, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1c s5 assertion time see note 3 ? ns 2eb assertion time see note 3 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 1.5t-2.44 1.5t-0.8 ns 5 address inactive after c s negated ? 0.3 ns 6d tack asserted after cs5 asserted ? 1019t ns 7d tack asserted to rw negated 2t+2.37 3t+6.6 ns 8 data hold timing after rw negated 1.5t-3.99 ? ns 9 data ready after cs5 is asserted ? t ns 10 cs deactive to next cs active t ? ns 11 eb negate after c s negate 0.5t 0.5t+0.5 ns 12 dtack pulse width 1t 3t ns note : 1. dtack asserted means d tack becomes low level. 2. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 3. cs5 assertion can be controlled by csa bits. eb assertion also can be programmed by wea bits in the cs5l register. 4. address becomes valid and rw asserts at the star t of write access cycle. 5.the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. oe dtack address eb cs5 rw (logic high) programmable min 0ns programmable min 0ns (output to i.mx) 3 8 5 4 6 10 7 11 12 1 2 9 databus
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 23 3.9.2.5 wait re ad cycle without dma figure 10. wait read cycle without dma table 17. wait read cycle without dma: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1oe and eb assertion time see note 2 ? ns 2cs5 pulse width 3t ? ns 3oe negated to address inactive 56.81 57.28 ns 4 wait asserted after oe asserted ? 1020t ns 5 wait asserted to oe negated 2t+1.57 3t+7.33 ns 6 data hold timing after oe negated t-1.49 ? ns 7 data ready after wait asserted 0 t ns 8 oe negated to cs negated 1.5t-0.68 1.5t-0.06 ns 9 oe negated after eb negated 0.06 0.18 ns 10 become low after cs5 asserted 0 1019t ns 11 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the star t of read access cycle. 4. the external wait input requirement is eliminated when cs5 is programmed to use internal wait state. wait address eb cs5 oe databus programmable min 0ns 1 2 3 8 9 5 6 7 11 10 4 (input to i.mx)
mc9328mxs advance information, rev. 0 24 freescale semiconductor specifications 3.9.2.6 wait re ad cycle dma enabled figure 11. wait read cycle dma enabled table 18. wait read cycle dma enab led: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1oe and eb assertion time see note 2 ? ns 2cs pulse width 3t ? ns 3oe negated before cs5 is negated 1.5t-0.68 1.5t-0.06 ns 4 address inactived before cs negated ? 0.05 ns 5 wait asserted after cs5 asserted ? 1020t ns 6wait asserted to oe negated 2t+1.57 3t+7.33 ns 7 data hold timing after oe negated t-1.49 ? ns 8 data ready after wait is asserted ? t ns 9cs deactive to next cs active t ns 10 oe negate after eb negate 0.06 0.18 ns 11 wait becomes low after cs5 asserted 0 1019t ns 12 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the star t of read access cycle. 4. the external wait input requirement is eliminated when cs5 is programmed to use internal wait state. rw wait address eb cs5 oe (logic high) databus programmable min 0ns 1 2 3 8 9 5 6 7 11 10 12 4 (input to i.mx)
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 25 3.9.2.7 wait write cycle without dma figure 12. wait write cycle without dma table 19. wait write cycle without dm a: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1cs5 assertion time see note 2 ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 2.5t-3.63 2.5t-1.16 ns 5rw negated to address inactive 64.22 ? ns 6 wait asserted after cs5 asserted ? 1020t ns 7 wait asserted to rw negated t+2.66 2t+7.96 ns 8 data hold timing after rw negated 2t+0.03 ? ns 9 data ready after cs5 is asserted ? t ns 10 eb negated after cs5 is negated 0.5t 0.5t+0.5 ns 11 wait becomes low after cs5 asserted 0 1019t ns 12 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (for 96 mhz system clock, t=10.42 ns) 2. cs5 assertion can be controlled by csa bits. eb assertion can also be programable by wea bits in cs5l register. 3. address becomes valid and rw asserts at the star t of write access cycle. 4. the external wait input requ irement is eliminated when cs5 is programmed to use internal wait state. oe wait address eb cs5 rw (logic high) databus programmable min 0ns programmable min 0ns 1 2 3 8 5 6 7 11 10 12 4 (output to i.mx) 9
mc9328mxs advance information, rev. 0 26 freescale semiconductor specifications 3.9.2.8 wait wri te cycle dma enabled figure 13. wait write cycle dma enabled table 20. wait write cycle dma enable d: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1 cs5 assertion time see note 2 ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 2.5t-3.63 2.5t-1.16 ns 5 address inactived after cs negated ? 0.09 ns 6 wait asserted after cs5 asserted ? 1020t ns 7 wait asserted to rw negated t+2.66 2t+7.96 ns 8 data hold timing after rw negated 2t+0.03 ? ns 9 data ready after cs5 is asserted ? t ns 10 cs deactive to next cs active t ? ns 11 eb negate after cs negate 0.5t 0.5t+0.5 12 wait becomes low after cs5 asserted 0 1019t ns 13 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. cs5 assertion can be controlled by csa bits. eb assertion also can be programable by wea bits in cs5l register. 3. address becomes valid and rw asserts at the start of write access cycle. 4.the external wait input requ irement is eliminated when cs5 is programmed to use internal wait state. oe wait address eb cs5 rw (logic high) databus programmable min 0ns programmable min 0ns 8 5 7 11 12 4 (output to i.mx) 1 2 3 10 6 13 9
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 27 3.9.3 eim external bus timing the following timing diagrams show the timi ng of accesses to memory or a peripheral. figure 14. wsc = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready bclk (burst clock) addr cs2 r/w lba oe ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) data read seq/nonseq v1 last valid data last valid address read v1 v1 v1 internal signals - shown on ly for illustrative purposes note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
mc9328mxs advance information, rev. 0 28 freescale semiconductor specifications figure 15. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1) bclk (burst clock) addr cs0 r/w lba oe eb data internal signals - shown onl y for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 29 figure 16. wsc = 1, oea = 1, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 0 r/w lba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
mc9328mxs advance information, rev. 0 30 freescale semiconductor specifications figure 17. wsc = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data bclk (burst clock) addr cs0 r/w lba oe eb data internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 31 figure 18. wsc = 3, oea = 2, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs [3] r/w ba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
mc9328mxs advance information, rev. 0 32 freescale semiconductor specifications figure 19. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 3 r/w lba oe data weim_hrdata eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 33 figure 20. wsc = 3, oea = 4, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe weim_data_in weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 34 freescale semiconductor specifications figure 21. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data hwdata eb weim_hrdata write nonseq v1 address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data last valid data internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 35 figure 22. wsc = 3, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
mc9328mxs advance information, rev. 0 36 freescale semiconductor specifications figure 23. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 37 figure 24. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 38 freescale semiconductor specifications figure 25. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 39 figure 26. wsc = 2, wws = 2, wea = 1, wen = 2, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 40 freescale semiconductor specifications figure 27. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 data hwdata last valid data write data read data write last valid data write data read write idle ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 41 figure 28. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data write data (1/2 half word) write data (2/2 half word) hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs r/w lba oe weim_hrdata eb data hwdata last valid data internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 42 freescale semiconductor specifications figure 29. wsc = 3, csa = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 4 r/w l ba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data data hwdata ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 43 figure 30. wsc = 2, oea = 2, cnc = 3, bcm = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 read data (v1) address v2 last valid last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2) ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 44 freescale semiconductor specifications figure 31. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read data hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 45 figure 32. wsc = 3, sync = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata nonseq nonse read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 46 freescale semiconductor specifications figure 33. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 47 figure 34. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb address v1 last valid read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 48 freescale semiconductor specifications figure 35. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 49 figure 36. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
mc9328mxs advance information, rev. 0 50 freescale semiconductor specifications 3.9.4 non-tft panel timing figure 37. non-tft panel timing ? vsyn, hsyn and sclk can be programmed as active high or active low. in the above timing diagram, all these 3 signals are active high. ? ts is the shift clock period. ? ts = tpix * (panel data bus width). ? tpix is the pixel clock period which equals lcdc_clk period * (pcd + 1). ? maximum frequency of lcdc_clk is 48 mhz, which is controlled by peripheral clock divider register. ? maximum frequency of sclk is hclk / 5, otherwise ld output will be wrong. table 21. non tft panel timing diagram symbol parameter allowed register minimum value actual value unit t1 hsyn to vsyn delay 0 hwait2+2 tpix t2 hsyn pulse width 0 hwidth+1 tpix t3 vsyn to sclk ? 0<= t3<=ts ? t4 sclk to hsyn 0 hwait1+1 tpix t1 t2 t4 t3 xmax vsyn sclk hsyn ld[15:0] t2 t1 ts
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 51 3.10 spi timing diagrams to use the internal transmit (tx) and receive (rx) data fifos when the spi module is configured as a master, two control signals are used for data transfer rate control: the ss signal (output) and the spi_rdy signal (input). the spi1 sample period control register (periodreg1) can al so be programmed to a fixed data transfer rate. when the spi module is configured as a slave, the user ca n configure the spi1 control register (controlreg1) to match the external spi master?s tim ing. in this co nfiguration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to in crement the data fifo. figure 38 through figure 42 show the timing relationship of the mast er spi using different triggering mechanisms. figure 38. master spi timing diagram using spi_rdy edge trigger figure 39. master spi timing diagram using spi_rdy level trigger figure 40. master spi timing diagram ignore spi_rdy level trigger figure 41. slave spi timing diag ram fifo advanced by bit count 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso
mc9328mxs advance information, rev. 0 52 freescale semiconductor specifications figure 42. slave spi timing diagram fifo advanced by ss rising edge 3.11 lcd controller this section includes timing diagrams for the lcd controller. for deta iled timing diagrams of the lcd controller with various display configurations, refe r to the lcd contro ller chapter of the i.mx reference manual . figure 43. sclk to ld timing diagram table 22. timing parameter table for figure 38 through figure 42 ref no. parameter 3.0 0.3 v unit minimum maximum 1 spi_rdy to ss output low 2t 1 1. t = cspi system clock period (perclk2). ?ns 2ss output low to first sclk edge 3 tsclk 2 2. tsclk = period of sclk. ?ns 3 last sclk edge to ss output high 2 tsclk ? ns 4ss output high to spi_rdy low 0 ? ns 5ss output pulse width tsclk + wait 3 3. wait = number of bit clocks (sclk) or 32.768 khz clocks per sample pe riod control register. ?ns 6ss input low to first sclk edge t ? ns 7ss input pulse width t ? ns table 23. lcdc sclk timing parameter table ref no. parameter 3.0 0.3 v unit minimum maximum 1 sclk to ld valid ? 2 ns 6 7 ss (input) sclk, mosi, miso 1 lsclk ld[15:0]
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 53 figure 44. 4/8/16 bit/pixe l tft color mode panel timing table 24. 4/8/16 bit/pixe l tft color mode panel timing symbol description minimum corresponding register value unit t1 end of oe to beginning of vsyn t5+t6 +t7+t9 (vwait1t2)+t5+t6+t7+t9 ts t2 hsyn period xmax+5 xm ax+t5+t6+t7+t9+t10 ts t3 vsyn pulse width t2 vwidth(t2) ts t4 end of vsyn to beginning of oe 2 vwait2(t2) ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to t9 1 hwait2+1 ts t7 end of oe to beginning of hsyn 1 hwait1+1 ts t8 sclk to valid ld data -3 3 ns t9 end of hsyn idle2 to vsyn edge (for non-display region) 22ts t9 end of hsyn idle2 to vsyn edge (for display region) 11ts line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax vsyn hsyn oe ld[15:0] sclk hsyn oe ld[15:0] t2 t8 vsyn t9 t10 display region non-display region line y
mc9328mxs advance information, rev. 0 54 freescale semiconductor specifications t10 vsyn to oe active (sharp = 0) when vwait2 = 0 1 1 ts t10 vsyn to oe active (sharp = 1) when vwait2 = 0 2 2 ts note: ts is the sclk period which equals lcdc_clk / (pcd + 1). normally lcdc_clk = 15ns. vsyn, hsyn and oe can be programmed as active high or active low. in figure 44, all 3 signals are active low. the polarity of sclk and ld[15:0] can also be programmed. sclk can be programmed to be deactivated during the vsyn pulse or the oe deasserted period. in figure 44, sclk is always active. for t9 non-display region, vsyn is non-active. it is us ed as an reference. xmax is defined in pixels. table 24. 4/8/16 bit/pixel tft co lor mode panel timing (continued) symbol description minimum corresponding register value unit
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 55 3.12 pulse-width modulator the pwm can be programmed to select one of two clock si gnals as its source frequency. the selected clock signal is passed through a divider and a prescaler before being inpu t to the counter. the output is available at the pulse- width modulator output (pwmo) external pin. its timing diagram is shown in figure 45 and the parameters are listed in table 25. figure 45. pwm output timing diagram table 25. pwm output timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 system clk frequency 1 1. c l of pwmo = 30 pf 0870100mhz 2a clock high time 1 3.3 ? 5/10 ? ns 2b clock low time 1 7.5 ? 5/10 ? ns 3a clock fall time 1 ?5?5/10ns 3b clock rise time 1 ?6.67?5/10ns 4a output delay time 1 5.7 ? 5 ? ns 4b output setup time 1 5.7 ? 5 ? ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a
mc9328mxs advance information, rev. 0 56 freescale semiconductor specifications 3.13 sdram controller this section shows timing diagrams and parameters associated with the sdram (synchronous dynamic random access memory) controller. figure 46. sdram read cycle timing diagram table 26. sdram read timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 3s cs, ras, cas, we, dqm setup time 3.42 ? 3 ? ns 3h cs, ras, cas, we, dqm hold time 2.28 ? 2 ? ns sdclk cs cas we ras addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6 note: cke is high during the read/write cycle.
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 57 4s address setup time 3.42 ? 3 ? ns 4h address hold time 2.28 ? 2 ? ns 5 sdram access time (cl = 3) ? 6.84 ? 6 ns 5 sdram access time (cl = 2) ? 6.84 ? 6 ns 5 sdram access time (cl = 1) ? 22 ? 22 ns 6 data out hold time 2.85 ? 2.5 ? ns 7 data out high-impedance time (cl = 3) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 2) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 1) ? 22 ? 22 ns 8 active to read/write command period (rc = 1) t rcd 1 ? t rcd 1 ?ns 1. t rcd = sdram clock cycle time. this settings can be found in the i.mx reference manual . table 26. sdram read timi ng parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
mc9328mxs advance information, rev. 0 58 freescale semiconductor specifications figure 47. sdram write cycle timing diagram table 27. sdram write timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period 1 t rp 2 ? t rp 2 ?ns 7 active to read/write command delay t rcd 2 ? t rcd 2 ?ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 59 figure 48. sdram refresh timing diagram 8 data setup time 4.0 ? 2 ? ns 9 data hold time 2.28 ? 2 ? ns 1. precharge cycle timing is included in the write timing diagram. 2. t rp and t rcd = sdram clock cycle time. these settings can be found in the i.mx reference manual . table 28. sdram refresh timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns table 27. sdram write timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7
mc9328mxs advance information, rev. 0 60 freescale semiconductor specifications figure 49. sdram self-refresh cycle timing diagram 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period t rp 1 ? t rp 1 ?ns 7 auto precharge command period t rc 1 ? t rc 1 ?ns 1. t rp and t rc = sdram clock cycle time. these settings can be found in the i.mx reference manual . table 28. sdram refresh timi ng parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum sdclk cs cas ras addr dq dqm ba we cke
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 61 3.14 usb device port four types of data transfer modes exis t for the usb module: contro l transfers, bulk transfers, isochronous transfers, and interrupt transfers. from the perspe ctive of the usb module, the interrupt tr ansfer type is identical to the bulk data transfer mode, and no additional ha rdware is supplied to support it. this section covers the transfer modes and how they work from the ground up. data moves across the usb in packets. groups of packets are combined to form data transfers. the same packet transfer mechanism applies to bulk, inte rrupt, and control transfers. isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fi xed portion of the usb bandwi dth at all times, there is no end-of-transfer. figure 50. usb device timing diagram for data transfer to usb transceiver (tx) table 29. usb device timing parameters for data transfer to usb transceiver (tx) ref no. parameter 3.0 0.3 v unit minimum maximum 1t roe_vpo ; usbd_roe active to usbd_vpo low 83.14 83.47 ns 2t roe_vmo ; usbd_roe active to usbd_vmo high 81.55 81.98 ns 3t vpo_roe ; usbd_vpo high to usbd_roe deactivated 83.54 83.80 ns 4t vmo_roe ; usbd_vmo low to usbd_roe deactivated (includes se0) 248.90 249.13 ns 5t feopt ; se0 interval of eop 160.00 175.00 ns 6t period ; data transfer rate 11.97 12.03 mb/s usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) usbd_suspnd (output) usbd_rcv (input) usbd_vp (input) usbd_vm (input) t roe_vpo t vmo_roe t vpo_roe t feopt t roe_vmo t period 1 2 3 4 5 6
mc9328mxs advance information, rev. 0 62 freescale semiconductor specifications figure 51. usb device timing diagram for data transfer from usb transceiver (rx) table 30. usb device timing parameter table for data transfer from usb transceiver (rx) ref no. parameter 3.0 0.3 v unit minimum maximum 1t feopr ; receiver se0 interval of eop 82 ? ns usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) (output) usbd_suspnd (input) usbd_vp usbd_rcv (input) usbd_vm (input) t feopr 1
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 63 3.15 i 2 c module the i 2 c communication protocol consists of seven elemen ts: start, data source/reci pient, data direction, slave acknowledge, data, data acknowledge, and stop. figure 52. definition of bus timing for i 2 c 3.16 synchronous serial interface the transmit and receive sections of the ssi can be sy nchronous or asynchronous. in synchronous mode, the transmitter and the receiver use a comm on clock and frame synchronization signal. in asynch ronous mode, the transmitter and receiver each have their own clock and frame synchroniza tion signals. continuous or gated clock mode can be selected. in continuous mode, the clock runs continuously. in gated clock mode, the clock functions only during transmission. the intern al and external clock timing diagrams are shown in figure 54 through figure 56 on page 65. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. use of the gated clock is not allowed in network mode. these distinctions result in the basic operating modes that allo w the ssi to communicate with a wide variety of devices. table 31. i 2 c bus timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 hold time (repeated) start condition 182 ? 160 ? ns 2 data hold time 01710150ns 3 data setup time 11.4 ? 10 ? ns 4 high period of the scl clock 80 ? 120 ? ns 5 low period of the scl clock 480 ? 320 ? ns 6 setup time for stop condition 182.4 ? 160 ? ns sda scl 1 2 3 4 6 5
mc9328mxs advance information, rev. 0 64 freescale semiconductor specifications note: srxd input in synchronous mode only. figure 53. ssi transmitter internal clock timing diagram figure 54. ssi receiver internal clock timing diagram stck output stfs (bl) output stfs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 srck output srfs (bl) output srfs (wl) output 3 7 srxd input 13 14 1 5 9
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 65 figure 55. ssi transmitter external clock timing diagram figure 56. ssi receiver ex ternal clock timing diagram table 32. ssi (port c primary function) timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum internal clock operation 1 (port c primary function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.54.51.33.9ns 3 srck high to srfs (bl) high 3 -1.2 -1.7 -1.1 -1.5 ns stck input 16 stfs (bl) input stfs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only 33 20 15 srck input 16 srfs (bl) input srfs (wl) input 17 19 23 srxd input 29 30 21 25 15
mc9328mxs advance information, rev. 0 66 freescale semiconductor specifications 4 stck high to stfs (bl) low 3 2.54.32.23.8ns 5 srck high to srfs (bl) low 3 0.1 -0.8 0.1 -0.8 ns 6 stck high to stfs (wl) high 3 1.48 4.45 1.3 3.9 ns 7 srck high to srfs (wl) high 3 -1.1 -1.5 -1.1 -1.5 ns 8 stck high to stfs (wl) low 3 2.51 4.33 2.2 3.8 ns 9 srck high to srfs (wl) low 3 0.1 -0.8 0.1 -0.8 ns 10 stck high to stxd valid from high impedance 14.25 15.73 12.5 13.8 ns 11a stck high to stxd high 0.91 3.08 0.8 2.7 ns 11b stck high to stxd low 0.57 3.19 0.5 2.8 ns 12 stck high to stxd high impedance 12.88 13.57 11.3 11.9 ns 13 srxd setup time before srck low 21.1 ? 18.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port c primary function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.01 28.16 15.8 24.7 ns 27a stck high to stxd high 8.98 18.13 7.0 15.9 ns 27b stck high to stxd low 9.12 18.24 8.0 16.0 ns 28 stck high to stxd high impedance 18.47 28.5 16.2 25.0 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns synchronous internal clock operation (port c primary function 2 ) 31 srxd setup before stck falling 15.4 ? 13.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns table 32. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
specifications mc9328mxs advance information, rev. 0 freescale semiconductor 67 synchronous external clock operation (port c primary function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted se rial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck an d/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 sets of i/o signals for the ssi module. they are from port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288). when ss i signals are configured as outputs, they can be viewed both at port c primary function and po rt b alternate function. when ssi sig nals are configured as input, the ssi module selects the input based on status of the fmcr register bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 33. ssi (port b alternat e function) timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum internal clock operation 1 (port b altern ate function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.1 1.0 -0.1 1.0 ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.1 1.0 -0.1 1.0 ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from high impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port b alternate function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns table 32. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
mc9328mxs advance information, rev. 0 68 freescale semiconductor specifications 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hold time after srck low 0 ? 0 ? ns synchronous internal clock operation (port b alternate function 2 ) 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port b alternate function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/ or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 set of i/o signals for the ssi module. they are from port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288). when ss i signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi sig nals are configured as inputs, the ssi module selects the input based on fmcr register bits in th e clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 33. ssi (port b alternate funct ion) timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
mc9328mxs advance information, rev. 0 freescale semiconductor 69 pin-out and package information 4 pin-out and package information table 34 illustrates the package pin assi gnments for the 225-contact pbga package. table 34. i.mx 225 pbga pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a pb13 ssi1_ rxclk ssi1_ txclk usbd_ roe usbd_ suspnd usbd_vm ssi0_ rxfs ssi0_ txclk spi1_rdy spi1_ sclk rev ps ld2 ld4 ld5 b pb11 pb12 ssi1_ rxdat usbd_ afe usbd_ rcv usbd_ vmo ssi0_ rxdat uart1_ txd spi1_ss lsclk spl_ spr ld0 ld3 ld6 ld7 c d31 pb8 ssi1_ rxfs ssi1_ txfs pb10 usbd_ vpo uart2_ rxd ssi0_ txfs uart1_ rts contrast vsync ld8 ld9 ld12 nvdd2 d a23 a24 pb9 ssi1_ txdat nvdd1 usbd_ vp qvdd4 uart2_ txd nvdd3 spi1_ mosi hsync ld1 ld11 tout2 ld13 e a21 a22 d30 d29 nvdd1 qvss uart2_ rts uart1_ rxd uart1_ cts spi1_ miso oe_ acd ld10 tin pa4 pa3 f a20 a19 d28 d27 nvdd1 nvdd1 uart2_ cts ssi0_ rxclk ssi0_ txdat cls qvdd3 ld14 ld15 pa6 pa8 g a17 a18 d26 d25 nvdd1 nvss nvdd4 nvss nvss qvss pwmo pa7 pa11 pa13 pa9 h a15 a16 d23 d24 d22 nvss nvss nvss nvss nvdd2 pa5 pa12 pa14 i2c_data tms j a14 a12 d21 d20 nvdd1 nvss nvss qvdd1 nvss pa10 i2c_ clk tck tdo boot1 boot0 k a13 a11 cs2 d19 nvdd1 nvss qvss nvdd1 nvss d1 boot2 tdi big_ endian reset_ out xtal32k l a10 a9 d17 d18 nvdd1 nvdd1 cs5 d2 ecb nvss nvss por qvss xtal16m extal32k m d16 d15 d13 d10 eb3 nvdd1 cs4 cs1 bclk 1 1. burst clock rw nvss boot3 qvdd2 reset_in extal16m n a8 a7 d12 eb0 d9 d8 cs3 cs0 pa17 d0 dqm2 dqm0 sdcke0 tristate trst p d14 a5 a4 a3 a2 a1 d6 d5 ma10 ma11 dqm1 ras sdcke1 clko resetsf 2 2. these signals are not used on the mc9328mxs and should be floated in an actual application. r a6 d11 eb1 eb2 oe d7 a0 sdclk 2 d4 lba d3 dqm3 cas sdwe avdd1
mc9328mxs advance information, rev. 0 70 freescale semiconductor pin-out and package information 4.1 pbga 225 package dimensions figure 57 illustrates the 225 pbga 13 mm 13 mm package. figure 57. i.mx processor?s 225 pbga mechanical drawing top view bottom view side view case outline 1304b notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane is defined by spherical crowns of the solder balls. 5. parallelism measurement shall exclude an y effect of mark on top surface of package.
mc9328mxs advance information, rev. 0 freescale semiconductor 71 notes
mc9328mxs/d rev. 0 1/2005 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor hong kong ltd. 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. learn more : for more information about freescale products, please visit www.freescale.com. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of thei r respective owners. arm and the arm powered logo are the registered trademarks of arm limited. arm9, arm920t, and arm9tdmi are the trademarks of arm limited. ? freescale semiconductor, inc. 2005. all rights reserved.

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